device info: Cyclone IV E , EP4CE40F23C8, speed grade 8, core voltage 1.2, pin count 484
bladeRF pin definition Under assignments - import assigments , use the csv file above (taken from the bladeRF project) note that the default pin assignment should be fixed up by the tcl script pins.tcl
create a new block design and call it as your top level design
Add new verilog hdl as follows
// This is an example of a simple 32 bit up-counter called simple_counter.v // It has a single clock input and a 32-bit output port module simple_counter (input clock , output reg [31:0] counter_out); always @ (posedge clock)// on positive clock edge begin counter_out <= #1 counter_out + 1;// increment counter end endmodule// end of module counter
Choose File > Create/Update > Create Symbol Files for Current File to convert the simple_counter.v file to a Symbol File (.sym). You use this Symbol File to add the HDL code to your BDF schematic.
Insert the above symbol in the board
Then insert the clock as in the tutorial
Connect the output for pll to the counter
The problem of incompatible voltage for io pins and banks, you have to have the nconfigured pin with the normal voltage, see Assignments- Device - device and pin options - Voltage
Power suply is divided in to "banks" the left (VCCIO_L_C4) and right VCCIO_R_C4. COnnector j38 is the acual debugger connector, possibly
FX3 part number CYUSB3014-BZXC
This is what I have understood so far
set_global_assignment -name QIP_FILE [file normalize [file join $here ../../ip/altera/pll/pll.qip]] set_global_assignment -name QSYS_FILE [file normalize [file join $here ../../ip/altera/nios_system/nios_system.qsys]] set_global_assignment -name QIP_FILE [file normalize [file join $here ../../ip/altera/rx_fifo/rx_fifo.qip]] set_global_assignment -name QIP_FILE [file normalize [file join $here ../../ip/altera/tx_fifo/tx_fifo.qip]] set_global_assignment -name QIP_FILE [file normalize [file join $here ../../ip/altera/serial_pll/serial_pll.qip]] # Explicitly include Nios mem_init set_global_assignment -name QIP_FILE [file normalize [file join $here ../../ip/altera/nios_system/software/lms_spi_controller/mem_init/meminit.qip]] # Implementation details set_global_assignment -name VHDL_FILE [file normalize [file join $here vhdl/ramp.vhd]] set_global_assignment -name VHDL_FILE [file normalize [file join $here vhdl/bladerf-hosted.vhd]] # SDC Constraints set_global_assignment -name SDC_FILE [file normalize [file join $here constraints/bladerf.sdc]]
then add the rest of definitions
set_global_assignment -name DEVICE EP4CE40F23C8 set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 set_global_assignment -name TOP_LEVEL_ENTITY bladerf set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files # Configuration settings set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "FAST PASSIVE PARALLEL" set_global_assignment -name USE_CONFIGURATION_DEVICE OFF set_global_assignment -name GENERATE_TTF_FILE ON set_global_assignment -name GENERATE_RBF_FILE ON set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "USE AS REGULAR IO" set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "USE AS REGULAR IO" set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" # Create an base revision set_global_assignment -name QIP_FILE [file normalize ../../fpga/platforms/bladerf/bladerf.qip] source [file normalize ../../fpga/platforms/bladerf/constraints/pins.tcl] export_assignments
key part is the bladerf.tcl script
Saved Sun Aug 25 10:05:40 CEST 2013